68000 Implementation of 32-Bit floating-Point Addition and Multiplication
Statement of the Problem
Implement a 68000 program that will determine the sum and the product of two 32-bit floating point numbers. Both floating point numbers are in the IEEE single-precision floating point format. The first operand is located in the memory address $100 and the second operand is located in memory address $104. the sum and the product should be placed in memory address $3000 and $3004 respectively. The program should start at address $2000. Inputs to the program should be placed in memory using assembler commands.
Implementation must utilize subroutines. All exceptions defined in the standard must be considered in this implementation.
Given a 32-bit floating point number in IEEE single precision format, operations like addition and multiplication can be simplified if both of the operand are decomposed into their mantissa and exponent. This can be done by copying the mantissa and the exponent from the original format using AND operation. The ANDed exponent must be shifted 23 bits to the right.
Once the exponent of the operands has been copied, it must be tested if it is Zero or equal to 255 (111111112). If it is zero and the mantissa is non-zero, it means that the operand is in ‘denormalized’ form and has to be normalized before performing add and multiply operations. Otherwise, if both mantissa and exponent are zero, the value it represents is zero. On the other hand, if the exponent is equal to 255, it represents either of the two special numbers, infinity and not a number (NaN). If the exponent is equal to 255 and the mantissa is equal to zero, its value is equal to either negative or positive infinity, depending on the sign. However, if the mantissa is equal to any non-zero number, the said operand is not a number (NaN). A subroutine must be utilize to handle such exceptions and special numbers.
After aligning the exponent of the smaller operand with respect to the bigger operand, the sign of the operands must be check to determine the appropriate operations to perform. If both operands have the same sign, either ‘1’ for negative or ‘0’ for positive, the sum can be performed by just adding their mantissas. Their corresponding sign is just the sign of either operand since they have the same sign. However, if one of the operand is negative and one is positive, the negative operand must be complemented first before performing addition. If the sum of the mantissa is negative, it must be complemented again to get the unsigned magnitude and mark the sign equal to ‘1’.
After addition, the sum must be normalized either by shifting the mantissa to the left until a bit ‘1’ is placed on the 24th bit or by shifting the mantissa one bit to the right if the 25th bit (this occurs if the exponents of the operands are equal). Any number of shifts of exponent to the left or right must correspond to the number of subtract or add to the exponent. The exponent must be check for underflow or overflow. If underflow or overflow occur, the program is terminated. Underflow occurs if the exponent if less than zero. Likewise, overflow occurs if the exponent of the sum exceeds 255.
After performing necessary operations on the exponent and mantissa of the sum, they must be combined into IEEE format. Combining the sign, exponent and mantissa can be done using OR instruction ones the sign, exponent and mantissa are already on their appropriate positions (32nd bit for sign, 31st to 24th bit for exponent and 23rd to 1st bit for mantissa). The bit ‘1’ on the 24th bit will be hidden.
If any or both the operands is zero and the other is a real number, the product is automatically zero and no need to undergo the whole multiplication procedure for real numbers.
The problem on performing multiplication is how to perform multiplication for 24-bit operands that utilize the longest possible 32-bit long word register since the product has a length of 64 bits
This problem can be solve by dividing the 32-bit operand into 2 16-bit operand and perform the operation illustrated by the following figure:
Figure 1: D1 stores the 32-bit MSB and D0 stores the 32-bit LSB
The exponent of the product is the sum of the exponents of the operands. A bias of 127 must be subtracted from the exponent. The sign of the product is just the XOR of the signs of the operands.
Same as in addition, the product must be normalized by shifting the mantissa until a bit ‘1’ is placed on the 24th bit of the 24 bit MSB of the product. Overflow and underflow must also be checked. Since only 23 bits are needed for IEEE format, the 24-bit LSB of the product must be truncated using ‘Von Neuman’ rounding method. ‘Von Neuman’ rounding just says that if atleast one of the truncated bits is ‘1’, the LSB of the remaining bits will be ‘1’ otherwise, no special changes will be performed. After performing such operations, combine the sign, exponent and mantissa into IEEE format just like in the case of addition.